| Low Power
| | |
| 2 | A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-μm CMOS Utilizing
Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration
| 2019 |  |
| 3 | Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-
Power IoT and Ultralow Phase-Noise Cellular Applications
| 2019 | |
| 4 | Multi loop Control for Fast Transient DC–DC Converter
| 2019 | |
| 5 | Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage
Regulation
| 2019 | |
| 6 | High speed and low power preset-able modified TSPC D flip-flop
design and performance comparison with TSPC D flip-flop
| 2019 | |
| 7 | A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC
| 2019 | |
| 8 | Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp
Stimulus Generator for On-Chip Static Linearity Test of ADCs
| 2019 | |
| 9 | A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in
0.18-μm CMOS | 2019 | |
| 10 | Analysis, Comparison, and Experimental Validation of a Class AB
Voltage Follower With Enhanced Bandwidth and Slew Rate | 2019 | |
| 11 | Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write
and Dropped-VDD Read for Power Reduction | 2019 | |
| 12 | Radiation-Hardened 14T SRAM Bit cell With Speed and Power
Optimized for Space Application | 2019 | |
| 13 | A Dynamic Timing Error Avoidance Technique Using Prediction Logic in
High-Performance Designs | 2019 | |
| 14 | Designing Efficient Circuits Based on Runtime-Reconfigurable Field-
Effect Transistors | 2019 | |
| 15 | Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-
Independent Read Port Leakage for Array Augmentation in 32-nm
CMOS | 2019 | |
| 16 | A Wideband Low-Noise Variable-Gain Amplifier with a 3.4 dB NF and
up to 45 dB gain tuning range in 130 nm CMOS | 2019 | |
| HIGH SPEED AND SIGNAL PROCESSING
| | |
| 1 | A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal
Common-Mode Control | 2019 | |
| 2 | An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time
Neural Recording With 0.175 μW/Channel in 65-nm CMOS | 2019 | |
| 3 | Feed forward-Cut set-Free Pipelined Multiply–Accumulate Unit for the
Machine Learning Accelerator | 2019 | |
| 4 | An Analog LO Harmonic Suppression Technique for SDR Receivers | 2019 | |
| 5 | CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency | 2019 | |
| 6 | Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock
Jitter, and ISI | 2019 | |
| 7 | Design of Reconfigurable Digital IF Filter with Low Complexity | 2019 | |
| 8 | Multiplier-free Implementation of Galois Field Fourier Transform on a
FPGA | 2019 | |
| 9 | Analysis and Optimization of Multi section Capacitive DACs for Mixed-
Signal Processing | 2019 | |
| 10 | A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G | 2019 | |
| 11 | A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With
2.43 ppm/°C Temperature Coefficient | 2019 | |
| 12 | An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid
for Digitally-Controlled Clock and Data Recovery Loops | 2019 | |
| 13 | An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid
for Digitally-Controlled Clock and Data Recovery Loops | 2019 | |
| 14 | Line Coding Techniques for Channel Equalization: Integrated Pulse-
Width Modulation and Consecutive Digit Chopping | 2019 | |
| 15 | Area–Delay–Energy Efficient VLSI Architecture for Scalable In-Place
Computation of FFT on Real Data | 2019 | |
| AREA EFFICIENT/ TIMING & DELAY REDUCTION
| | |
| 1 | A High-Throughput Hardware Accelerator for Lossless Compression of
a DDR4 Command Trace | 2019 | |
| 2 | Multistage Linear Feedback Shift Register Counters With Reduced
Decoding Logic in 130-nm CMOS for Large-Scale Array Applications | 2019 | |
| 3 | A Decoder for Short BCH Codes With High Decoding Efficiency and
Low Power for Emerging Memories | 2019 | |
| 4 | Area–Delay–Energy Efficient VLSI Architecture for Scalable In-Place
Computation of FFT on Real Data | 2019 | |
| 5 | Rapid Balise Telegram Decoder with Modified LFSR Architecture for
Train Protection Systems | 2019 | |
| 6 | Area-Time Efficient Streaming Architecture for FAST and BRIEF
Detector | 2019 | |
| 7 | Efficient Design for Fixed-Width Adder-Tree | 2019 | |
| 8 | An Energy-efficient Accelerator based on Hybrid CPU-FPGA
Devices for Password Recovery | 2019 | |
| 9 | Chaos-Based Bitwise Dynamical Pseudorandom Number Generator on
FPGA | 2019 | |
| 10 | A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial
Carry-Save Radix-8 Booth Multipliers in Data paths | 2019 | |
| 11 | Hardware-Efficient Post-processing Architectures for True Random
Number Generators | 2019 | |
| 12 | New Majority Gate Based Parallel BCD Adder Designs for Quantumdot
Cellular Automata | 2019 | |
| 13 | Power Efficient Approximate Multipliers in LMS Adaptive Filters | 2019 | |
