Vlsi IEEE Projects 2017-2018
Vlsi IEEE Projects 2017-2018, Vlsi IEEE Projects Titles 2017-2018. We are offering ieee projects 2017-2018 in latest technology like Java ieee projects, dotnet ieee projects, android ieee projects, embedded ieee projects, embedded diploma projects, embedded mini projects, matlab ieee projects, digital image processing ieee projects, dip ieee projects, vlsi ieee projects, hadoop ieee projects, power electronics ieee projects, power system ieee projects, mechanical final year projects, mechanical diploma projects, mechanical mini projects, civil final year projects projects, MBA Final year projects. IEEE Master is a unit of LeMeniz Technologies. We guide all final year M.E/M.Tech, B.E/B.Tech, MPhil, MCA, BCA, M.Sc, B.Sc, and Diploma students for their Academic Projects to get best results.
S.No | Code | IEEE Based on LOW POWER | Year |
---|---|---|---|
A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging | |||
Adaptive Multi-bit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication | |||
Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture | |||
Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding | |||
Resource-Efficient SRAM-based Ternary Content Addressable Memory | |||
Resource-Efficient SRAM-based Ternary Content Addressable Memory | |||
Write-Amount-Aware Management Policies for STT-RAM Caches | |||
Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA | |||
High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder | |||
High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations | |||
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST | |||
Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map |
S.No | Code | IEEE Based on HIGH SPEED DATA TRANSMISSION | Year |
---|---|---|---|
Efficient Designs of Multi-ported Memory on FPGA | |||
High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA | |||
An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock | |||
A 2.4–3.6-GHz Wideband Sub-harmonically Injection-Locked PLL with Adaptive Injection Timing Alignment Technique | |||
Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares | |||
Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm | |||
A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission | |||
Scalable Device Array for Statistical Characterization of BTI-Related Parameters |
S.No | Code | IEEE Based on Audio, Image and Video Processing | Year |
---|---|---|---|
A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding | |||
RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing | |||
Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations | |||
Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers | |||
An FPGA-Based Hardware Accelerator for Traffic Sign Detection | |||
Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations | |||
Time-Encoded Values for Highly Efficient Stochastic Circuits | |||
Design of Power and Area Efficient Approximate Multipliers |
S.No | Code | IEEE Based on VERIFICATION | Year |
---|---|---|---|
COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits | |||
Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction |
S.No | Code | IEEE Based on NETWORKING | Year | Download |
---|---|---|---|---|
Multicast-Aware High-Performance Wireless Network-on-Chip Architectures |
S.No | Code | IEEE Based on VLSI - BACK END PROJECT - TANNER(nm) / HSPICE(nm) / DSCH3 - MICROWIND(um) | Year |
---|---|---|---|
Temporarily Fine-Grained Sleep Technique for Near- and Sub-threshold Parallel Architectures | |||
Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique | |||
Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator | |||
10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage | |||
Delay Analysis for Current Mode Threshold Logic Gate Designs | |||
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications | |||
Probability-Driven Multi-bit Flip-Flop Integration With Clock Gating | |||
A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications | |||
A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS | |||
Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application | |||
An All-MOSFET Sub-1-V Voltage Reference With a−51-dB PSR up to 60 MHz | |||
A Novel Methodology to Acquire Live Big Data Evidence from the Cloud | |||
A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy | |||
Temporarily Fine-Grained Sleep Technique for Near- and Sub-threshold Parallel Architectures | |||
A 100-mA, 99.11% Current Efficiency, 2-mVppRipple Digitally Controlled LDO with Active Ripple Suppression | |||
Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template | |||
On Micro-architectural Mechanisms for Cache Wear out Reduction | |||
Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology | |||
A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing | |||
A 0.45 V 147–375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures |
Vlsi IEEE Projects 2017-2018
Vlsi IEEE Projects 2017-2018, Vlsi IEEE Projects titles 2017-2018. We are offering ieee projects 2017-2018 in latest technology like Java ieee projects, dot net ieee projects, android ieee projects, ns2 ieee projects, embedded ieee projects, matlab ieee projects, digital image processing ieee projects, vlsi ieee projects, hadoop ieee projects, power elctronics ieee projects, power system ieee projects, mechanical ieee projects, civil projects ieee project. We guide all final year M.E/M.Tech, B.E/B.Tech, MPhil, MCA, BCA, M.Sc, B.Sc, and Diploma students for their Academic Projects to get best results. We are offering java ieee projects in pondicherry. LeMeniz Technologies is a new class of software concern committed to catalyzing the competence and competitiveness of its clients by helping them succeed through the power of information technology. Driven by the credo that solutions are effective only when organizational needs are accurately ascertained and aptly addressed; LeMeniz Infotech looks upon itself as an integral part of its client’s organization. We have varied and extensive expertise in software development, web portal development, application software development, e-commerce website development, mobile application development, search engine optimization, bulk sms services, social media marketing, ieee projects guidance and more.