VLSI IEEE Projects 2016-2017

VLSI IEEE Projects 2016-2017

Vlsi IEEE Projects 2016-2017, Vlsi IEEE Projects Titles 2016-2017. We are offering ieee projects 2016-2017 in latest technology like Java ieee projects, dotnet ieee projects, android ieee projects, embedded ieee projects, matlab ieee projects, digital image processing ieee projects, vlsi ieee projects, hadoop ieee projects, power electronics ieee projects, power system ieee projects, mechanical ieee projects, civil projects ieee projects. IEEE Master is a unit of LeMeniz Technologies. We guide all final year M.E/M.Tech, B.E/B.Tech, MPhil, MCA, BCA, M.Sc, B.Sc, and Diploma students for their Academic Projects to get best results.

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S.No

Code

IEEE Based on Low Power

Year

1
LM_VL_LP016_01
A Fully Digital Front-End Architecture for ECG Acquisition System with 0.5v Supply
2016
2
LM_VL_LP016_02
Low-Cost High Performance VLSI Architecture for Montgomery Modular Multiplication
2016
3
LM_VL_LP016_03
RF Power Gating: A Low-Power Technique for Adaptive Radios
2016
4
LM_VL_LP016_04
A New Parallel VLSI Architecture for Real-Time Electrical Capacitance Tomography
2016
5
LM_VL_LP016_05
Low-Power FPGA Design Using Memoization-Based Approximate Computing
2016
6
LM_VL_LP016_06
Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units
2016
7
LM_VL_LP016_07
A 3-D CPU-FPGA_DRAM Hybrid architecture for Low-Power Computation
2016
8
LM_VL_LP016_08
Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs
2016
9
LM_VL_LP016_09
Flexible ECC Management for Low-Cost Transient Error Protection of Last-Level Caches
2016

S.No

Code

IEEE Based on High Speed Data Transmission

Year

1
LM_VL_HS016_01
A High-Speed FPGA Implementation of an RSD-Based ECC Processor
2016
2
LM_VL_HS016_02
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
2016
3
LM_VL_HS016_03
A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling
2016
4
LM_VL_HS016_04
Code Compression for Embedded Systems Using Separated Dictionaries
2016
5
LM_VL_HS016_05
A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding
2016
6
LM_VL_HS016_06
Design and Implementation of High-Speed All-Pass Transformation- Based Variable Digital Filters by Breaking the Dependence of Operating Frequency on Filter Order
2016
7
LM_VL_HS016_07
Statistical Framework and Built-In Self Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators
2016
8
LM_VL_HS016_08
A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit Design for In-Ear Headphones
2016
9
LM_VL_HS016_09
Source Coding and Preemphasis for Double-Edged Pulse width Modulation Serial Communication
2016
10
LM_VL_HS016_10
A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register
2016
11
LM_VL_HS016_11
GPU-Accelerated Parallel Sparse LU Factorization Method for Fast Circuit Analysis
2016
12
LM_VL_HS016_12
An All-Digital Approach to Supply Noise Cancellation in Digital Phase- Locked Loop
2016
13
LM_VL_HS016_13
Design of Modified Second-Order Frequency Transformations Based Variable Digital Filters With Large Cutoff Frequency Range and Improved Transition Band Characteristics
2016

S.No

Code

IEEE Based on Area Efficienct / Timing & Delay Reduction

Year

1
LM_VL_AE016_01
A Mixed-Decimation MDF Architecture for Radix-2K Parallel FFT
2016
2
LM_VL_AE016_02
Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications With Convolution Codes
2016
3
LM_VL_AE016_03
One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements
2016
4
LM_VL_AE016_04
Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers
2016
5
LM_VL_AE016_05
Hybrid LUT/Multiplexer FPGA Logic Architectures
2016
6
LM_VL_AE016_06
Implementing Minimum-Energy-Point Systems With Adaptive Logic
2016
7
LM_VL_AE016_07
High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m)
2016
8
LM_VL_AE016_08
LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter
2016
9
LM_VL_AE016_09
Graph-Based Transistor Network Generation Method for Supergate Design
2016
10
LM_VL_AE016_10
Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic
2016
11
LM_VL_AE016_11
A Cellular Network Architecture With Polynomial Weight Functions
2016
12
LM_VL_AE016_12
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
2016
13
LM_VL_AE016_13
Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks
2016
14
LM_VL_AE016_14
Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors
2016
15
LM_VL_AE016_15
A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO
2016
16
LM_VL_AE016_16
Low-Power/Cost RNS Comparison via Partitioning the Dynamic Range
2016
17
LM_VL_AE016_17
Understanding the Relation Between the Performance and Reliability of NAND Flash/SCM Hybrid Solid-State Drive
2016
18
LM_VL_AE016_18
Optimized Built-In Self-Repair for Multiple Memories
2016
19
LM_VL_AE016_19
Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest
2016
20
LM_VL_AE016_20
A High-Throughput Hardware Design of a One-Dimensional SPIHT Algorithm
2016
21
LM_VL_AE016_21
Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation
2016
22
LM_VL_AE016_22
Speculative Look ahead for Energy-Efficient Microprocessors
2016
23
LM_VL_AE016_23
Efficient Synchronization for Distributed Embedded Multiprocessors
2016
24
LM_VL_AE016_24
NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices
2016
25
LM_VL_AE016_25
A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies
2016
26
LM_VL_AE016_26
A New Optimal Algorithm for Energy Saving in Embedded System With Multiple Sleep Modes
2016
27
LM_VL_AE016_27
A Fast Fault-Tolerant Architecture for Sauvola Local Image Thresholding Algorithm Using Stochastic Computing
2016
28
LM_VL_AE016_28
Efficiency Enablers of Lightweight SDR for MIMO Baseband Processing
2016
29
LM_VL_AE016_29
A Novel Quantum-Dot Cellular Automata X-bit ×32-bit SRAM
2016
30
LM_VL_AE016_30
Ultralow-Energy Variation-Aware Design: Adder Architecture Study
2016
31
LM_VL_AE016_31
Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems
2016
32
LM_VL_AE016_32
Toward Solving Multichannel RF-SoC Integration Issues Through Digital Fractional Division
2016
33
LM_VL_AE016_33
Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching
2016
34
LM_VL_AE016_34
Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation
2016
35
LM_VL_AE016_35
On Efficient Retiming of Fixed-Point Circuits
2016
36
LM_VL_AE016_36
Trigger-Centric Loop Mapping on CGRAs
2016
37
LM_VL_AE016_37
Area-Aware Cache Update Trackers for Post silicon Validation
2016
38
LM_VL_AE016_38
PEVA: A Page Endurance Variance Aware Strategy for the Lifetime Extension of NAND Flash
2016
39
LM_VL_AE016_39
Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures
2016
40
LM_VL_AE016_40
An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code
2016
41
LM_VL_AE016_41
Concept, Design, and Implementation of Reconfigurable CORDIC
2016

S.No

Code

IEEE Based on Networking

Year

1
LM_VL_NW016_01
In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers
2016
2
LM_VL_NW016_02
FCUDA-NoC : A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow
2016
3
LM_VL_NW016_03
Process Variation Delay and Congestion Aware Routing Algorithm for Asynchronous NoC Design
2016
4
LM_VL_NW016_04
Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation
2016
5
LM_VL_NW016_05
Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems
2016
6
LM_VL_NW016_06
A New CDMA Encoding/Decoding Method for on-Chip Communication Network
2016

S.No

Code

IEEE Based on Tanner & Microwind/DSCH3

Year

1
LM_VL_NW016_01
A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell
2016
2
LM_VL_NW016_02
OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application
2016
3
LM_VL_NW016_03
A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All- Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects
2016
4
LM_VL_TN016_04
Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation
2016
5
LM_VL_TN016_05
A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS
2016
6
LM_VL_TN016_06
A Systematic Design Methodology of Asynchronous SAR ADCs
2016
7
LM_VL_TN016_07
Read Bit line Sensing and Fast Local Write-Back Techniques in Hierarchical Bit line Architecture for Ultralow-Voltage SRAMs
2016
8
LM_VL_TN016_08
Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs
2016
9
LM_VL_TN016_09
Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence
2016
10
LM_VL_TN016_10
PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices
2016
11
LM_VL_TN016_11
A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM
2016
12
LM_VL_TN016_12
Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization
2016
13
LM_VL_TN016_13
Dual-Calibration Technique for Improving Static Linearity of Thermometer DACs for I/O
2016
14
LM_VL_TN016_14
An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers
2016
15
LM_VL_TN016_15
SRAM-Based Unique Chip Identifier Techniques
2016
16
LM_VL_TN016_16
A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits
2016
17
LM_VL_TN016_17
Low-Power Variation-Tolerant Nonvolatile Lookup Table Design
2016
18
LM_VL_TN016_18
Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM
2016
19
LM_VL_TN016_19
Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators
2016
20
LM_VL_TN016_20
High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator
2016
21
LM_VL_TN016_21
EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control
2016
22
LM_VL_TN016_22
A Single-Stage Low-Dropout Regulator With a Wide Dynamic Range for Generic Applications
2016
23
LM_VL_TN016_23
Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits
2016

S.No

Code

IEEE Based on Audio, Image & Video Processing

Year

1
LM_VL_AU016_01
Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
2016
2
LM_VL_AU016_02
A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing
2016
3
LM_VL_AU016_03
A New Binary-Halved Clustering Method and ERT Processor for ASSR System
2016
4
LM_VL_AU016_04
The VLSI Architecture of a Highly Efficient De-blocking Filter for HEVC Systems
2016

Vlsi IEEE Projects 2016-2017

Vlsi IEEE Projects 2016-2017, Vlsi IEEE Projects titles 2016-2017. We are offering ieee projects 2016-2017 in latest technology like Java ieee projects, dot net ieee projects, android ieee projects, ns2 ieee projects, embedded ieee projects, matlab ieee projects, digital image processing ieee projects, vlsi ieee projects, hadoop ieee projects, power elctronics ieee projects,  power system ieee projects, mechanical ieee projects, civil projects ieee project. We guide all final year M.E/M.Tech, B.E/B.Tech, MPhil, MCA, BCA, M.Sc, B.Sc, and Diploma students for their Academic Projects to get best results. We are offering java ieee projects in pondicherry. LeMeniz Infotech is a new class of software concern committed to catalyzing the competence and competitiveness of its clients by helping them succeed through the power of information technology. Driven by the credo that solutions are effective only when organizational needs are accurately ascertained and aptly addressed; LeMeniz Infotech looks upon itself as an integral part of its client’s organization. We have varied and extensive expertise in software development, web portal development, application software development, e-commerce website development, mobile application development, search engine optimization, bulk sms services, social media marketing, ieee projects guidance and more.

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